Authors: Susil Kumar Mohanty and Siba Kumar Udgata

Authors: Susil Kumar Mohanty and Somanath Tripathy

In today's cryptocurrency, the Payment Channel Network (PCN) is noticed as one of the most gifted off-chain solutions for scalability issues. Besides this, it consumes lesser transaction fees and low transaction confirmation time. However, security and privacy issues need to be addressed appropriately to make the solution even more effective. Most of the existing HTLC (Hashed Time-Lock Contract) protocols revealed the sender's information to the intermediate users in the payment route. In this work, we propose an effective secure and privacy-preserving Payment Channel Network protocol, named Neo Hashed Time-Lock Commitment (n-HTLC) protocol. (n-HTLC) does not require the sender to send any information to each intermediate user along the payment route, thus preserves the identity of the sender. But, (n-HTLC) is not compatible with Sphinx onion packet format. Therefore, a symmetric key encryption-based protocol called k-TLC has been proposed. k-TLC is compatible with the Sphinx onion packet format, which is used in the current Lightning network atop of the Bitcoin blockchain network. The security of both n-HTLC and kTLC are proved using the Universal Composability (UC) framework. It is observed that both ensure that no attacker can extract information on the payment route if at least one of the users in the path is honest. To analyze the performance of both n-HTLC and kTLC payment protocol, we conduct experiments using the snapshots of Ripple network, Lightning network, and synthetic network of CryptoMaze. Our experimental results show that both n-HTLC and kTLC outperform state-of-the-art off-chain payment protocols in terms of computational and communication overhead.

Authors: Susil Kumar Mohanty and Siba Kumar Udgata

Now in the era of the Internet of Energy (IoE), researchers are more focused on optimal energy utilization. In the wireless sensor network, maximization of battery lifetime or network lifetime is one of the primary research objectives. There are many techniques available to enhance the network lifetime, and interference minimization is one of them. Interference minimization leads to less transmission power consumption in wireless sensor networks and thus enhances the network lifetime. The interference minimization is proven to be NP-Hard problem. In this paper, we have proposed a method to minimize receiver interference using different encoding schemes and genetic algorithm. We have used more realistic probabilistic interference model to calculate receiver interference instead of the graph-based model used in most of the literature. The Genetic Algorithm used to minimize receiver interference uses three different chromosome representation schemes, namely Prüfer code, Edge-set, and Edge-window-decoder. We have used benchmark data sets and special cases like exponential node chain, two exponential node chain, spiral model, one cluster, and two-cluster for experimental simulations. Our proposed algorithm outperforms other algorithms available in the literature like MI-S (Minimizing Interference in Sensor networks), MinMax-RIP (Minimizing Maximum Receiver Interference Problem), and MST (Minimum Spanning Tree: Prim’s algorithm) in terms of minimizing maximum receiver interference in the network.

Authors: Somanath Tripathy and Susil Kumar Mohanty

Payment channel network (PCN) has become an indispens-able mechanism to resolve scalability issues in blockchain-based cryp-tocurrencies. On the other hand, PCNs do not provide adequate securityand privacy guarantee. Most of the existing payment schemes leak in-formation about payer or payee to the nodes in the payment path. Toaddress this issue, we propose a simple but effective, multi-hop, anony-mous, and privacy-preserving PCN(MAPPCN). MAPPCN constructionis based on Elliptic curve cryptography (ECC) and is proved to be securewhile achieving payment path privacy, sender, and receiver anonymity.MAPPCN can be performed in (3·n+ 5) Elliptic curve scalar multipli-cation (ECSM) operations for an off-chain payment operation.

Authors: B. N. Bhramar Ray, Sony Singdha Sahoo, and Susil Kumar Mohanty

G-NSVF: A Greedy Algorithm for Non-slicing VLSI Floorplanning

Authors: B. N. Bhramar Ray, Sony Singdha Sahoo, Rasheswari Bhramar Ray, and Susil Kumar Mohanty

Analytical placer very often uses half-perimeter wirelength (HPWL) model as an objective function for solving placement problem. State-of-the-art iterative wirelength models for HPWL are log-sum-exp (LSE) [1], weighted average (WA) [2], (γ, q) [3] and CHMAX [4] wirelength models. In this paper, we propose an iterative wirelength model for HPWL providing smooth approximation to max function. The new max function is the difference of two convex functions. The error upper bound of proposed model is tighter than upper bound errors of existing iterative wirelength models. Integration of new model in analytical placement engine NTUplacer, reduces the final placement wirelength by 13%, 10%, 3% and 1.5% on an average on ISPD 2005 benchmark circuits as oppose to LSE, WA, (γ, q) and CHMAX models respectively.

Authors: B. N. Bhramar Ray, Susil Kumar Mohanty, Debabrat Sethy, and Rasheswari Bhramar Ray

Placement is a crucial stage in the physical design of VLSI(Very Large Scale Integration). Analytical placer at this stage determines optical physical locations of cells in the chip while minimizing the total half-perimeter wirelength(HPWL) of the nets. The constraints imposed while minimizing the total HPWL of nets are non-overlapping of blocks, congestion, delay etc. This paper introduces a recursive smooth wirelength model for HPWL of a net using Gaussian error function, which can be used by analytical placers. The novelty of this model lies in approximating closely the HPWL of a net than other state-of-the-art wirelength models in the literature including log-sum-exponent(LSE), weighted average(WA), CHMAX and absolute wirelength(ABSWL) models. The HPWL accuracy of the proposed model for global and detailed placements for IBM ISPD 2004 benchmark suite shows less than 1% and 0.5% absolute errors in total wirelength in average respectively.

Authors: B. N. Bhramar Ray, S. Das, K. Hazra, N. Patra, and Susil Kumar Mohanty

In VLSI physical design, placement is an important stage. Analytical placer minimizes the half-perimeter wire lengh (HPWL) of the circuit as an objective function to place blocks optimally in the chip. This paper introduces a new smooth recursive model for HPWL function which can be used inside the analytical placers. The proposed model is more accurate than widely used log-sum-exponent (LSE)[9], weighted average (WA)[3] and ABSWL[7] models. The error upper bound of new approximation is also tightest among the existing wire length models. When deployed inside placement engine NUPlacer[1], it shows reduction in wire lengh by 12.3%, 10% and 3% on ISPD 2005 placement benchmarks compared to LSE, WA and ABSWL models respectively.

Ph. D. Term Project

Blockchain has been solution to many existing problems. It has established trust among stakeholders. Blockchain in education will bring speed, privacy along with instant validation and security. In education, automation of awarding credits, intellectual property rights, preventing piracy, authenticating trusted source and job based on informal education can be achieved by blockchain. This paper surveys other key areas where blockchain can contribute. Consortium blockchain can add benefits for faster exchange and more secure storage. Our proposed work is a process for verification of educational certificates, when a student applying for higher studies or job. We have used public key cryptography for privacy-preserving and standard prover-verifier technique for verification to achieve sharing education credits without disclosing confidential information.

M. Tech Project

The transmission power assignment and scheduling length minimization both are proven to be NP-Hard. In this project, we are using SINR (Signal to Interference plus Noise Ratio) model for considering successful data packet transmission with minimum transmission power and scheduling. Assignment of optimal transmission power is a very difficult problem for this, we have developed some heuristics to assignment transmission power to each and every requests (or all sensor nodes are interested to transmit simultaneously) with minimum k-number of schedules according to MAC protocol. For minimizing total transmission power consumption and scheduling length, we have used Genetic Algorithm with two chromosome representation schemes (I. Edge-List, and II. Edge-window Decoder) with considering real sensor data sheet parameters. The current simulation shows positive gains in transmission power and scheduling lengths.

M. Sc. Project

Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, etc. Considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. To construct an initial connectivity graph we use a novel Territory-Obstacle Avoiding Spanning Graph (T-OASG) construction algorithm using partially Dynamic Programming techniques. Most of the cases the runtime complexity of our algorithm is O(k log k), where k = {1, 2, 3, ........, n}, but some cases (end of the chip dimension) the complexity of our algorithm is O(n log n).